| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2026-01-04 | finish disassembler | uvok | |
| 2026-01-04 | finish disasseembler | uvok | |
| 2026-01-04 | disas: move arg check in main | uvok | |
| 2026-01-04 | black format | uvok | |
| 2026-01-04 | disas: lowercase ops, arg decode | uvok | |
| main | |||
| 2026-01-04 | decode op and jumps | uvok | |
| 2026-01-04 | Start by bin creator and disassembler | uvok | |
| 2026-01-03 | ins: Add flags to docu | uvok | |
| 2026-01-03 | finish instruction decoder testbench | uvok | |
| 2026-01-03 | document nandgame/HACK | uvok | |
| 2026-01-02 | id testbench | uvok | |
| 2026-01-02 | Rename variables to be more clear, document | uvok | |
| 2026-01-02 | prepare instruction decode tb | uvok | |
| 2026-01-02 | add include guard to memory | uvok | |
| 2026-01-02 | Add nandgame computer | uvok | |
| 2026-01-02 | Fix verilator multi-module warning | uvok | |
| 2026-01-02 | docu | uvok | |
| 2026-01-02 | finish instruction decoder | uvok | |
| support immediates | |||
| 2026-01-01 | add instruction decoder | uvok | |
| 2026-01-01 | fix verilator fuckup | uvok | |
| some recent version of verilator in oss-cad-build-suite started adding_tb to the filename. | |||
| 2026-01-01 | try to implement comb_mem | uvok | |
| 2026-01-01 | don't delete vvp files | uvok | |
| 2026-01-01 | fix cunter, add testbench | uvok | |
| 2026-01-01 | Add counter | uvok | |
| 2026-01-01 | Add nandgame condition check | uvok | |
| 2026-01-01 | Update,implement ALU test | uvok | |
| 2026-01-01 | alu: Fix assignment error | uvok | |
| 2026-01-01 | include types in tbs again | uvok | |
| 2026-01-01 | tbs: remove e empty parens | uvok | |
| 2026-01-01 | Invert u | uvok | |
| 2026-01-01 | add ALU | uvok | |
| 2026-01-01 | fix comment | uvok | |
| 2026-01-01 | guard types | uvok | |
| 2026-01-01 | Add arithmetic unit, disable gtkwave | uvok | |
| 2026-01-01 | Add nandgame files | uvok | |
| need/want systemverilog | |||
| 2026-01-01 | remove superfluous ws | uvok | |
| 2026-01-01 | Add nandgame save | uvok | |
| 2025-12-30 | linting, use different naming | uvok | |
| use _tb.v instead of .tb.v, to stop verilator from shouting the module name doesn't match | |||
| 2025-12-30 | template: Introduce nedge | uvok | |
| 2025-12-30 | tst_delay: Fix testbench name | uvok | |
| 2025-12-30 | Fix testbench | uvok | |
| 2025-12-30 | fizzbuzz: Fix testbench | uvok | |
| also, remove testing output | |||
| 2025-12-30 | led_tgl_bounce:Fix testbench | uvok | |
| same aswith the others | |||
| 2025-12-30 | led_toggle: Use edge timing, logic | uvok | |
| 2025-12-30 | p2s2p: Fix testbench | uvok | |
| iverilog syntax error (needs space) timing use logic, | |||
| 2025-12-30 | my_mem: Use nededge for timing | uvok | |
| 2025-12-30 | p2s: Fix test bench | uvok | |
| use negedge timing | |||
| 2025-12-30 | s2p: Fix testbench | uvok | |
| needed data valid signal | |||
| 2025-12-30 | make: shut up gtkwave | uvok | |
| 2025-12-29 | Add fucked test bench | uvok | |
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |