fpga-exper - FPGA experiments

Age	Commit message (Collapse)	Author
8 days	disas: lowercase ops, arg decode	uvok
	main
8 days	decode op and jumps	uvok

8 days	Start by bin creator and disassembler	uvok

9 days	ins: Add flags to docu	uvok

9 days	finish instruction decoder testbench	uvok

9 days	document nandgame/HACK	uvok

10 days	id testbench	uvok

10 days	Rename variables to be more clear, document	uvok

10 days	prepare instruction decode tb	uvok

10 days	add include guard to memory	uvok

10 days	Add nandgame computer	uvok

10 days	Fix verilator multi-module warning	uvok

10 days	docu	uvok

10 days	finish instruction decoder	uvok
	support immediates
11 days	add instruction decoder	uvok

11 days	fix verilator fuckup	uvok
	some recent version of verilator in oss-cad-build-suite started adding_tb to the filename.
11 days	try to implement comb_mem	uvok

11 days	don't delete vvp files	uvok

11 days	fix cunter, add testbench	uvok

11 days	Add counter	uvok

11 days	Add nandgame condition check	uvok

11 days	Update,implement ALU test	uvok

11 days	alu: Fix assignment error	uvok

11 days	include types in tbs again	uvok

11 days	tbs: remove e empty parens	uvok

11 days	Invert u	uvok

11 days	add ALU	uvok

11 days	fix comment	uvok

11 days	guard types	uvok

11 days	Add arithmetic unit, disable gtkwave	uvok

11 days	Add nandgame files	uvok
	need/want systemverilog
11 days	remove superfluous ws	uvok

11 days	Add nandgame save	uvok

13 days	linting, use different naming	uvok
	use _tb.v instead of .tb.v, to stop verilator from shouting the module name doesn't match
13 days	template: Introduce nedge	uvok

13 days	tst_delay: Fix testbench name	uvok

13 days	Fix testbench	uvok

13 days	fizzbuzz: Fix testbench	uvok
	also, remove testing output
13 days	led_tgl_bounce:Fix testbench	uvok
	same aswith the others
13 days	led_toggle: Use edge timing, logic	uvok

13 days	p2s2p: Fix testbench	uvok
	iverilog syntax error (needs space) timing use logic,
13 days	my_mem: Use nededge for timing	uvok

13 days	p2s: Fix test bench	uvok
	use negedge timing
13 days	s2p: Fix testbench	uvok
	needed data valid signal
13 days	make: shut up gtkwave	uvok

14 days	Add fucked test bench	uvok

14 days	mem: Add debug for iverilog	uvok

14 days	Fix fifo using memory, fix test bench	uvok

14 days	make,verilator: Use 4 make jobs	uvok

14 days	Add memory	uvok