fpga-exper - FPGA experiments

Age	Commit message (Collapse)	Author
8 hours	Add verilator linting	uvok

34 hours	make: Add flags to iverilog	uvok
	support g2012 for assertions
38 hours	make: make yosys-dep quit, add nextpnr_opts	uvok

40 hours	Add simulation targets	uvok

40 hours	makefile: centralize nextpnr args	uvok
	also, get roid ofPROGRAM variable
2 days	Use variables for device and family	uvok

2 days	Add clock constraints file	uvok

3 days	Add error for "used but no driver"	uvok

3 days	yosys: Use less specialized regex for error	uvok

3 days	Make conflicting drivers an error	uvok

3 days	Use yosys for dep generation after all	uvok

3 days	Write my own dep resolve script	uvok

3 days	Remove explicit synth and deps rule	uvok
	explicit rule prevents it from being an intermediate file
3 days	makefile: Finally fix makefiles?	uvok

3 days	makefile: Try fix dep rule	uvok

3 days	Massiely reorganize makefile	uvok
	- intermediate targets - helper targets - automatic deps file
3 days	Fix flash target to use PROGRAM variable	uvok

3 days	add show command	uvok

3 days	Don't write to persistant flash	uvok

3 days	Adjst Makefile	uvok
	- add dependency - Make PROGRAM variable
4 days	Write placed and routed SVGs	uvok

4 days	Use pattern	uvok

4 days	Add FPGA basics	uvok