| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 46 hours | remove missing include | uvok | |
| 4 days | Add halt state and flag | uvok | |
| 4 days | eater: Combine counting in prev. state | uvok | |
| save 1 cycle, as explained in video. also, only print lo->hi clk states to term. | |||
| 4 days | eater: Add subtract flag | uvok | |
| 4 days | eater: Print most control signals | uvok | |
| 4 days | eater,sim: Make decoder state actually public-flar | uvok | |
| 4 days | eater: Add verilator/cmake project | uvok | |
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index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |