| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2026-01-25 | eater: fix iverilog errors | uvok | |
| b/c of OUT name clashes | |||
| 2026-01-25 | eater: Add flags_in flag | uvok | |
| 2026-01-25 | eater: Horizontal flag display | uvok | |
| 2026-01-23 | eater, ncur: Put in more info, add disas | uvok | |
| 2026-01-23 | Add ncurses and disassembly | uvok | |
| 2026-01-22 | eater: PC inc included, decode on negedge | uvok | |
| Some cycles can be saved. As previously (wrongly) committed, the PC can be incremented early, but the decoder needs to do this "early", so as now implemented, on the falling clock adge already. | |||
| 2026-01-22 | Implement JMP | uvok | |
| and get rid of arbitrary run limitation. | |||
| 2026-01-22 | Implement LDI | uvok | |
| 2026-01-22 | Implement STA | uvok | |
| 2026-01-22 | Put instructions into std::vector | uvok | |
| 2026-01-21 | remove missing include | uvok | |
| 2026-01-21 | eater: Use correct opcodes | uvok | |
| I was off-by-one? | |||
| 2026-01-19 | Add halt state and flag | uvok | |
| 2026-01-19 | eater: Combine counting in prev. state | uvok | |
| save 1 cycle, as explained in video. also, only print lo->hi clk states to term. | |||
| 2026-01-19 | eater: Add subtract flag | uvok | |
| 2026-01-19 | eater: Print most control signals | uvok | |
| 2026-01-19 | eater,sim: Make decoder state actually public-flar | uvok | |
| 2026-01-19 | eater,sim: Reformat and extract func | uvok | |
| 2026-01-19 | eater: Add verilator/cmake project | uvok | |
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |