fpga-exper - FPGA experiments

Age	Commit message (Collapse)	Author
10 hours	eater, ncur: Put in more info, add disasmain	uvok

11 hours	Add ncurses and disassembly	uvok

35 hours	eater: PC inc included, decode on negedge	uvok
	Some cycles can be saved. As previously (wrongly) committed, the PC can be incremented early, but the decoder needs to do this "early", so as now implemented, on the falling clock adge already.
36 hours	Implement JMP	uvok
	and get rid of arbitrary run limitation.
36 hours	Implement LDI	uvok

36 hours	Implement STA	uvok

36 hours	Put instructions into std::vector	uvok

2 days	remove missing include	uvok

2 days	eater: Use correct opcodes	uvok
	I was off-by-one?
4 days	Add halt state and flag	uvok

4 days	eater: Combine counting in prev. state	uvok
	save 1 cycle, as explained in video. also, only print lo->hi clk states to term.
5 days	eater: Add subtract flag	uvok

5 days	eater: Print most control signals	uvok

5 days	eater,sim: Make decoder state actually public-flar	uvok

5 days	eater,sim: Reformat and extract func	uvok

5 days	eater: Add verilator/cmake project	uvok