| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 5 days | eater: Make ALUresult verilator-public | uvok | |
| 6 days | eater: Use separate "zbuffer" module | uvok | |
| keeps code a bit cleaner | |||
| 7 days | (System)Verilog: Be explicit about wire/logic | uvok | |
| 7 days | eater: Use "actual -" for alu | uvok | |
| better synthesis? | |||
| 7 days | eater_alu: Use 2complneg instead of subtract | uvok | |
| 7 days | eater: Add ALU | uvok | |
| while doing so, add always_out port for regs | |||
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |