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2026-01-25eater: decoder uses ALU flagsuvok
2026-01-25eater: ALU outputs flagsuvok
2026-01-25eater: fix iverilog errorsuvok
b/c of OUT name clashes
2026-01-22eater: PC inc included, decode on negedgeuvok
Some cycles can be saved. As previously (wrongly) committed, the PC can be incremented early, but the decoder needs to do this "early", so as now implemented, on the falling clock adge already.
2026-01-19Add halt state and flaguvok
2026-01-19eater: Add subtract flaguvok
2026-01-19eater: Add logic to switch between manual and automatic flagsuvok
2026-01-19eater: Use control flag struct in computeruvok
2026-01-19Add instruction decoder with FSMuvok
2026-01-18eater: Make bs a tri0uvok
because eater_computer has pull-downs on bus
2026-01-18eater: Add OUT reguvok
2026-01-18eater: documentuvok
2026-01-18eater: Test more signalsuvok
2026-01-18eater:PC clock runs on neg clockuvok
2026-01-18eater: Use separate "zbuffer" moduleuvok
keeps code a bit cleaner
2026-01-17eater: Add PC, fix signals for MEM/ADR, add readmeuvok
2026-01-16Add RAM and RAM_ADR registeruvok
2026-01-16eater: Connect RAMuvok
2026-01-16eater: Include RAMuvok
2026-01-16eater: Extract computer testbenchuvok
2026-01-16eater_alu: Use 2complneg instead of subtractuvok
2026-01-16eater: Add ALUuvok
while doing so, add always_out port for regs
2026-01-16Better tb for eater cpuuvok
2026-01-15Add instruction registeruvok
2026-01-15Add 1st sketch of eater cpuuvok
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