| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 5 days | eater: Add OUT reg | uvok | |
| 6 days | eater: document | uvok | |
| 6 days | eater: Test more signals | uvok | |
| 6 days | eater:PC clock runs on neg clock | uvok | |
| 6 days | eater: Use separate "zbuffer" module | uvok | |
| keeps code a bit cleaner | |||
| 6 days | eater: Add PC, fix signals for MEM/ADR, add readme | uvok | |
| 7 days | Add RAM and RAM_ADR register | uvok | |
| 7 days | eater: Connect RAM | uvok | |
| 7 days | eater: Include RAM | uvok | |
| 7 days | eater: Extract computer testbench | uvok | |
| 7 days | eater_alu: Use 2complneg instead of subtract | uvok | |
| 7 days | eater: Add ALU | uvok | |
| while doing so, add always_out port for regs | |||
| 8 days | Better tb for eater cpu | uvok | |
| 8 days | Add instruction register | uvok | |
| 8 days | Add 1st sketch of eater cpu | uvok | |
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |