| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2026-01-22 | eater: PC inc included, decode on negedge | uvok | |
| Some cycles can be saved. As previously (wrongly) committed, the PC can be incremented early, but the decoder needs to do this "early", so as now implemented, on the falling clock adge already. | |||
| 2026-01-19 | Add halt state and flag | uvok | |
| 2026-01-19 | eater: Add subtract flag | uvok | |
| 2026-01-19 | eater: Add logic to switch between manual and automatic flags | uvok | |
| 2026-01-19 | eater: Use control flag struct in computer | uvok | |
| 2026-01-19 | Add instruction decoder with FSM | uvok | |
| 2026-01-18 | eater: Make bs a tri0 | uvok | |
| because eater_computer has pull-downs on bus | |||
| 2026-01-18 | eater: Add OUT reg | uvok | |
| 2026-01-18 | eater: document | uvok | |
| 2026-01-18 | eater: Test more signals | uvok | |
| 2026-01-18 | eater:PC clock runs on neg clock | uvok | |
| 2026-01-18 | eater: Use separate "zbuffer" module | uvok | |
| keeps code a bit cleaner | |||
| 2026-01-17 | eater: Add PC, fix signals for MEM/ADR, add readme | uvok | |
| 2026-01-16 | Add RAM and RAM_ADR register | uvok | |
| 2026-01-16 | eater: Connect RAM | uvok | |
| 2026-01-16 | eater: Include RAM | uvok | |
| 2026-01-16 | eater: Extract computer testbench | uvok | |
| 2026-01-16 | eater_alu: Use 2complneg instead of subtract | uvok | |
| 2026-01-16 | eater: Add ALU | uvok | |
| while doing so, add always_out port for regs | |||
| 2026-01-16 | Better tb for eater cpu | uvok | |
| 2026-01-15 | Add instruction register | uvok | |
| 2026-01-15 | Add 1st sketch of eater cpu | uvok | |
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index : fpga-exper | |
| FPGA experiments |
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