fpga-exper - FPGA experiments

Age	Commit message (Collapse)	Author
22 hours	eater: PC inc included, decode on negedgemain	uvok
	Some cycles can be saved. As previously (wrongly) committed, the PC can be incremented early, but the decoder needs to do this "early", so as now implemented, on the falling clock adge already.
4 days	Add halt state and flag	uvok

4 days	eater: Add subtract flag	uvok

4 days	eater: Add logic to switch between manual and automatic flags	uvok

4 days	eater: Use control flag struct in computer	uvok

4 days	Add instruction decoder with FSM	uvok

5 days	eater: Make bs a tri0	uvok
	because eater_computer has pull-downs on bus
5 days	eater: Add OUT reg	uvok

5 days	eater: document	uvok

5 days	eater: Test more signals	uvok

5 days	eater:PC clock runs on neg clock	uvok

5 days	eater: Use separate "zbuffer" module	uvok
	keeps code a bit cleaner
6 days	eater: Add PC, fix signals for MEM/ADR, add readme	uvok

7 days	Add RAM and RAM_ADR register	uvok

7 days	eater: Connect RAM	uvok

7 days	eater: Include RAM	uvok

7 days	eater: Extract computer testbench	uvok

7 days	eater_alu: Use 2complneg instead of subtract	uvok

7 days	eater: Add ALU	uvok
	while doing so, add always_out port for regs
7 days	Better tb for eater cpu	uvok

8 days	Add instruction register	uvok

8 days	Add 1st sketch of eater cpu	uvok