fpga-exper - FPGA experiments

Age	Commit message (Collapse)	Author
36 hours	eater: PC inc included, decode on negedge	uvok
	Some cycles can be saved. As previously (wrongly) committed, the PC can be incremented early, but the decoder needs to do this "early", so as now implemented, on the falling clock adge already.
37 hours	Get rid of JMP_NOP	uvok

37 hours	Implement JMP	uvok
	and get rid of arbitrary run limitation.
38 hours	Implement LDI	uvok

38 hours	Implement STA	uvok

38 hours	Implement sub instruction	uvok

3 days	eater: Use correct opcodes	uvok
	I was off-by-one?
3 days	Revert "eater: Combine counting in prev. state"	uvok
	This reverts commit 1f0fc1edcea04e5c1f04803f0bdda337c2245f09.
5 days	Add halt state and flag	uvok

5 days	eater: Combine counting in prev. state	uvok
	save 1 cycle, as explained in video. also, only print lo->hi clk states to term.
5 days	eater,sim: Make decoder state actually public-flar	uvok

5 days	eater: Implement leftover states and state transitions	uvok

5 days	eater: Add logic to switch between manual and automatic flags	uvok

5 days	eater: Use control flag struct in computer	uvok

5 days	Add instruction decoder with FSM	uvok