| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2026-01-25 | eater: Add flags_in flag | uvok | |
| 2026-01-22 | eater: PC inc included, decode on negedge | uvok | |
| Some cycles can be saved. As previously (wrongly) committed, the PC can be incremented early, but the decoder needs to do this "early", so as now implemented, on the falling clock adge already. | |||
| 2026-01-22 | Get rid of JMP_NOP | uvok | |
| 2026-01-22 | Implement JMP | uvok | |
| and get rid of arbitrary run limitation. | |||
| 2026-01-22 | Implement LDI | uvok | |
| 2026-01-22 | Implement STA | uvok | |
| 2026-01-22 | Implement sub instruction | uvok | |
| 2026-01-21 | eater: Use correct opcodes | uvok | |
| I was off-by-one? | |||
| 2026-01-21 | Revert "eater: Combine counting in prev. state" | uvok | |
| This reverts commit 1f0fc1edcea04e5c1f04803f0bdda337c2245f09. | |||
| 2026-01-19 | Add halt state and flag | uvok | |
| 2026-01-19 | eater: Combine counting in prev. state | uvok | |
| save 1 cycle, as explained in video. also, only print lo->hi clk states to term. | |||
| 2026-01-19 | eater,sim: Make decoder state actually public-flar | uvok | |
| 2026-01-19 | eater: Implement leftover states and state transitions | uvok | |
| 2026-01-19 | eater: Add logic to switch between manual and automatic flags | uvok | |
| 2026-01-19 | eater: Use control flag struct in computer | uvok | |
| 2026-01-19 | Add instruction decoder with FSM | uvok | |
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index : fpga-exper | |
| FPGA experiments |
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