| Age | Commit message (Expand) | Author |
|---|---|---|
| 7 days | (System)Verilog: Be explicit about wire/logic | uvok |
| 7 days | eater: Add ALU | uvok |
| 7 days | Better tb for eater cpu | uvok |
| 8 days | eater: reg data out en is async | uvok |
| 8 days | Add 1st sketch of eater cpu | uvok |
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |