| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 7 days | (System)Verilog: Be explicit about wire/logic | uvok | |
| 7 days | eater: Add ALU | uvok | |
| while doing so, add always_out port for regs | |||
| 7 days | Better tb for eater cpu | uvok | |
| 8 days | eater: reg data out en is async | uvok | |
| 8 days | Add 1st sketch of eater cpu | uvok | |
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index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |