| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 22 hours | eater: PC inc included, decode on negedgemain | uvok | |
| Some cycles can be saved. As previously (wrongly) committed, the PC can be incremented early, but the decoder needs to do this "early", so as now implemented, on the falling clock adge already. | |||
| 23 hours | Implement JMP | uvok | |
| and get rid of arbitrary run limitation. | |||
| 23 hours | Implement LDI | uvok | |
| 23 hours | Implement STA | uvok | |
| 46 hours | Document SUB command | uvok | |
| 46 hours | eater: Use correct opcodes | uvok | |
| I was off-by-one? | |||
| 46 hours | Explain separate PC++ state | uvok | |
| need to get correct next state, once INS is loaded. | |||
| 4 days | Add halt state and flag | uvok | |
| 4 days | eater: Combine counting in prev. state | uvok | |
| save 1 cycle, as explained in video. also, only print lo->hi clk states to term. | |||
| 5 days | eater: update docs | uvok | |
| 6 days | eater: Add PC, fix signals for MEM/ADR, add readme | uvok | |
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index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |