fpga-exper - FPGA experiments

Age	Commit message (Expand)	Author
4 days	eater: Implement leftover states and state transitions	uvok
4 days	eater: Add logic to switch between manual and automatic flags	uvok
4 days	eater: Use control flag struct in computer	uvok
4 days	Add instruction decoder with FSM	uvok
4 days	Fix eater_types for Icarus	uvok
4 days	Add typer, preparation for SM	uvok
5 days	eater: update docs	uvok
5 days	eater: Add simpc makefile snippet	uvok
5 days	eater: Make ALUresult verilator-public	uvok
5 days	eater: Make bs a tri0	uvok
5 days	eater: Add OUT reg	uvok
5 days	eater: document	uvok
5 days	eater: Test more signals	uvok
5 days	eater:PC clock runs on neg clock	uvok
5 days	eater: Use separate "zbuffer" module	uvok
6 days	Add zbuffer spec	uvok
6 days	eater: Add PC, fix signals for MEM/ADR, add readme	uvok
7 days	Add RAM and RAM_ADR register	uvok
7 days	eater: Connect RAM	uvok
7 days	eater: Include RAM	uvok
7 days	(System)Verilog: Be explicit about wire/logic	uvok
7 days	eater: Use "actual -" for alu	uvok
7 days	eater: Extract computer testbench	uvok
7 days	eater_alu: Use 2complneg instead of subtract	uvok
7 days	eater: Add ALU	uvok
7 days	Better tb for eater cpu	uvok
8 days	Add instruction register	uvok
8 days	eater: reg data out en is async	uvok
8 days	Add 1st sketch of eater cpu	uvok