| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2026-01-16 | (System)Verilog: Be explicit about wire/logic | uvok | |
| 2026-01-16 | eater: Use "actual -" for alu | uvok | |
| better synthesis? | |||
| 2026-01-16 | eater: Extract computer testbench | uvok | |
| 2026-01-16 | eater_alu: Use 2complneg instead of subtract | uvok | |
| 2026-01-16 | eater: Add ALU | uvok | |
| while doing so, add always_out port for regs | |||
| 2026-01-16 | Better tb for eater cpu | uvok | |
| 2026-01-15 | Add instruction register | uvok | |
| 2026-01-15 | eater: reg data out en is async | uvok | |
| 2026-01-15 | Add 1st sketch of eater cpu | uvok | |
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index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |