| Age | Commit message (Expand) | Author |
|---|---|---|
| 6 days | eater: Add PC, fix signals for MEM/ADR, add readme | uvok |
| 7 days | Add RAM and RAM_ADR register | uvok |
| 7 days | eater: Connect RAM | uvok |
| 7 days | eater: Include RAM | uvok |
| 7 days | (System)Verilog: Be explicit about wire/logic | uvok |
| 7 days | eater: Use "actual -" for alu | uvok |
| 7 days | eater: Extract computer testbench | uvok |
| 7 days | eater_alu: Use 2complneg instead of subtract | uvok |
| 7 days | eater: Add ALU | uvok |
| 7 days | Better tb for eater cpu | uvok |
| 8 days | Add instruction register | uvok |
| 8 days | eater: reg data out en is async | uvok |
| 8 days | Add 1st sketch of eater cpu | uvok |
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |