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AgeCommit message (Expand)Author
2026-01-25tb: Check ALU Flaguvok
2026-01-25eater: Set ALU flagsuvok
2026-01-25eater: cpu tb: Add missing tb flaguvok
2026-01-25eater: decoder uses ALU flagsuvok
2026-01-25eater: ALU outputs flagsuvok
2026-01-25eater: fix iverilog errorsuvok
2026-01-25eater: Add flags_in flaguvok
2026-01-25eater: Horizontal flag displayuvok
2026-01-23eater, ncur: Put in more info, add disasuvok
2026-01-23Add ncurses and disassemblyuvok
2026-01-22eater: PC inc included, decode on negedgeuvok
2026-01-22Get rid of JMP_NOPuvok
2026-01-22Implement JMPuvok
2026-01-22Implement LDIuvok
2026-01-22Implement STAuvok
2026-01-22Put instructions into std::vectoruvok
2026-01-22Implement sub instructionuvok
2026-01-21Document SUB commanduvok
2026-01-21remove missing includeuvok
2026-01-21eater: Use correct opcodesuvok
2026-01-21Explain separate PC++ stateuvok
2026-01-21Revert "eater: Combine counting in prev. state"uvok
2026-01-19Add halt state and flaguvok
2026-01-19eater: Combine counting in prev. stateuvok
2026-01-19eater: Add subtract flaguvok
2026-01-19eater: Print most control signalsuvok
2026-01-19eater,sim: Make decoder state actually public-flaruvok
2026-01-19eater,sim: Reformat and extract funcuvok
2026-01-19eater: Add verilator/cmake projectuvok
2026-01-19eater: Implement leftover states and state transitionsuvok
2026-01-19eater: Add logic to switch between manual and automatic flagsuvok
2026-01-19eater: Use control flag struct in computeruvok
2026-01-19Add instruction decoder with FSMuvok
2026-01-19Fix eater_types for Icarusuvok
2026-01-19Add typer, preparation for SMuvok
2026-01-18eater: update docsuvok
2026-01-18eater: Add simpc makefile snippetuvok
2026-01-18eater: Make ALUresult verilator-publicuvok
2026-01-18eater: Make bs a tri0uvok
2026-01-18eater: Add OUT reguvok
2026-01-18eater: documentuvok
2026-01-18eater: Test more signalsuvok
2026-01-18eater:PC clock runs on neg clockuvok
2026-01-18eater: Use separate "zbuffer" moduleuvok
2026-01-18Add zbuffer specuvok
2026-01-17eater: Add PC, fix signals for MEM/ADR, add readmeuvok
2026-01-16Add RAM and RAM_ADR registeruvok
2026-01-16eater: Connect RAMuvok
2026-01-16eater: Include RAMuvok
2026-01-16(System)Verilog: Be explicit about wire/logicuvok
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