fpga-exper - FPGA experiments

Age	Commit message (Collapse)	Author
4 days	Add typer, preparation for SM	uvok

5 days	eater: update docs	uvok

5 days	eater: Add simpc makefile snippet	uvok

5 days	eater: Make ALUresult verilator-public	uvok

5 days	eater: Make bs a tri0	uvok
	because eater_computer has pull-downs on bus
5 days	eater: Add OUT reg	uvok

5 days	eater: document	uvok

5 days	eater: Test more signals	uvok

5 days	eater:PC clock runs on neg clock	uvok

5 days	eater: Use separate "zbuffer" module	uvok
	keeps code a bit cleaner
5 days	Add zbuffer spec	uvok
	remove "debug_bus"
6 days	eater: Add PC, fix signals for MEM/ADR, add readme	uvok

7 days	Add RAM and RAM_ADR register	uvok

7 days	eater: Connect RAM	uvok

7 days	eater: Include RAM	uvok

7 days	(System)Verilog: Be explicit about wire/logic	uvok

7 days	eater: Use "actual -" for alu	uvok
	better synthesis?
7 days	eater: Extract computer testbench	uvok

7 days	eater_alu: Use 2complneg instead of subtract	uvok

7 days	eater: Add ALU	uvok
	while doing so, add always_out port for regs
7 days	Better tb for eater cpu	uvok

8 days	Add instruction register	uvok

8 days	eater: reg data out en is async	uvok

8 days	Add 1st sketch of eater cpu	uvok