| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 13 days | linting, use different naming | uvok | |
| use _tb.v instead of .tb.v, to stop verilator from shouting the module name doesn't match | |||
| 14 days | Fix fifo using memory, fix test bench | uvok | |
| 2025-12-29 | Shut up verilators timescale warnings | uvok | |
| 2025-12-29 | fifo :Split in blocks | uvok | |
| 2025-12-29 | fifo: r/w/address logic | uvok | |
| 2025-12-29 | fifo: try implement r/w logic | uvok | |
| 2025-12-29 | fifo: Count bytes | uvok | |
| 2025-12-28 | add fifo | uvok | |
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |