| Age | Commit message (Expand) | Author |
|---|---|---|
| 7 hours | veri: Fix linting errors | uvok |
| 2 days | led: rename vars to make more sense | uvok |
| 3 days | clkdiv: output must be a register | uvok |
| 3 days | Make clock divider separate module | uvok |
| 4 days | Add FPGA basics | uvok |
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |