| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 3 days | clkdiv: output must be a register | uvok | |
| 3 days | Make clock divider separate module | uvok | |
| 4 days | Add FPGA basics | uvok | |
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |
|
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |
| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 3 days | clkdiv: output must be a register | uvok | |
| 3 days | Make clock divider separate module | uvok | |
| 4 days | Add FPGA basics | uvok | |