| Age | Commit message (Expand) | Author |
|---|---|---|
| 13 days | Shut up verilators timescale warnings | uvok |
| 2025-12-27 | veri: Fix linting errors | uvok |
| 2025-12-25 | led: rename vars to make more sense | uvok |
| 2025-12-24 | clkdiv: output must be a register | uvok |
| 2025-12-24 | Make clock divider separate module | uvok |
| 2025-12-23 | Add FPGA basics | uvok |
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index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |