| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 13 days | linting, use different naming | uvok | |
| use _tb.v instead of .tb.v, to stop verilator from shouting the module name doesn't match | |||
| 13 days | my_mem: Use nededge for timing | uvok | |
| 14 days | Add memory | uvok | |
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |
path: root/my_mem.tb.v