fpga-exper - FPGA experiments

Age	Commit message (Collapse)	Author
22 hours	fix olde makefile	uvok

23 hours	Dumpfile on VERILATOR	uvok
	get rid of VERILATE
23 hours	Reorganize cpp files	uvok

47 hours	verilator: Enable tracing	uvok

3 days	make: Unified makefile	uvok

4 days	makefile: Add instruction for simulated PC	uvok

6 days	make: Use variables for suffixes	uvok

11 days	fix verilator fuckup	uvok
	some recent version of verilator in oss-cad-build-suite started adding_tb to the filename.
11 days	don't delete vvp files	uvok

11 days	Add arithmetic unit, disable gtkwave	uvok

11 days	Add nandgame files	uvok
	need/want systemverilog