| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 4 days | makefile: Add instruction for simulated PC | uvok | |
| 6 days | make: Use variables for suffixes | uvok | |
| 11 days | fix verilator fuckup | uvok | |
| some recent version of verilator in oss-cad-build-suite started adding_tb to the filename. | |||
| 11 days | don't delete vvp files | uvok | |
| 11 days | Add arithmetic unit, disable gtkwave | uvok | |
| 11 days | Add nandgame files | uvok | |
| need/want systemverilog | |||
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index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |