| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 12 days | fix olde makefile | uvok | |
| 13 days | Dumpfile on VERILATOR | uvok | |
| get rid of VERILATE | |||
| 13 days | Reorganize cpp files | uvok | |
| 14 days | verilator: Enable tracing | uvok | |
| 2026-01-09 | make: Unified makefile | uvok | |
| 2026-01-08 | makefile: Add instruction for simulated PC | uvok | |
| 2026-01-06 | make: Use variables for suffixes | uvok | |
| 2026-01-01 | fix verilator fuckup | uvok | |
| some recent version of verilator in oss-cad-build-suite started adding_tb to the filename. | |||
| 2026-01-01 | don't delete vvp files | uvok | |
| 2026-01-01 | Add arithmetic unit, disable gtkwave | uvok | |
| 2026-01-01 | Add nandgame files | uvok | |
| need/want systemverilog | |||
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index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |