| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 14 hours | fix olde makefile | uvok | |
| 15 hours | Dumpfile on VERILATOR | uvok | |
| get rid of VERILATE | |||
| 16 hours | Reorganize cpp files | uvok | |
| 40 hours | verilator: Enable tracing | uvok | |
| 2 days | make: Unified makefile | uvok | |
| 3 days | makefile: Add instruction for simulated PC | uvok | |
| 6 days | make: Use variables for suffixes | uvok | |
| 10 days | fix verilator fuckup | uvok | |
| some recent version of verilator in oss-cad-build-suite started adding_tb to the filename. | |||
| 10 days | don't delete vvp files | uvok | |
| 10 days | Add arithmetic unit, disable gtkwave | uvok | |
| 10 days | Add nandgame files | uvok | |
| need/want systemverilog | |||
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index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |