| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 7 days | (System)Verilog: Be explicit about wire/logic | uvok | |
| 2026-01-07 | Annozate stuff for verilator | uvok | |
| publicly accessible | |||
| 2026-01-02 | Rename variables to be more clear, document | uvok | |
| 2026-01-02 | Fix verilator multi-module warning | uvok | |
| 2026-01-01 | alu: Fix assignment error | uvok | |
| 2026-01-01 | Invert u | uvok | |
| 2026-01-01 | add ALU | uvok | |
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |