| Age | Commit message (Expand) | Author |
|---|---|---|
| 4 days | Annozate stuff for verilator | uvok |
| 9 days | Rename variables to be more clear, document | uvok |
| 10 days | Fix verilator multi-module warning | uvok |
| 11 days | alu: Fix assignment error | uvok |
| 11 days | Invert u | uvok |
| 11 days | add ALU | uvok |
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |