| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 5 days | Annozate stuff for verilator | uvok | |
| publicly accessible | |||
| 10 days | Rename variables to be more clear, document | uvok | |
| 11 days | Fix verilator multi-module warning | uvok | |
| 11 days | alu: Fix assignment error | uvok | |
| 11 days | Invert u | uvok | |
| 11 days | add ALU | uvok | |
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |