| Age | Commit message (Expand) | Author |
|---|---|---|
| 7 days | (System)Verilog: Be explicit about wire/logic | uvok |
| 2026-01-02 | Rename variables to be more clear, document | uvok |
| 2026-01-02 | Fix verilator multi-module warning | uvok |
| 2026-01-01 | fix comment | uvok |
| 2026-01-01 | Add arithmetic unit, disable gtkwave | uvok |
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index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |