| Age | Commit message (Expand) | Author |
|---|---|---|
| 7 days | (System)Verilog: Be explicit about wire/logic | uvok |
| 12 days | comb_mem: Use async data o | uvok |
| 2026-01-09 | move stuff around | uvok |
| 2026-01-06 | use full address space | uvok |
| 2026-01-06 | include guards | uvok |
| 2026-01-02 | Rename variables to be more clear, document | uvok |
| 2026-01-02 | docu | uvok |
| 2026-01-01 | try to implement comb_mem | uvok |
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |