| Age | Commit message (Expand) | Author |
|---|---|---|
| 6 days | counter: Add "count_enable" pin | uvok |
| 7 days | (System)Verilog: Be explicit about wire/logic | uvok |
| 13 days | Use sync output for ROM | uvok |
| 13 days | CPU: Annotate unconnected pin | uvok |
| 13 days | Dumpfile on VERILATOR | uvok |
| 14 days | Implement halting | uvok |
| 2026-01-09 | move stuff around | uvok |
| 2026-01-07 | Annozate stuff for verilator | uvok |
| 2026-01-06 | use full address space | uvok |
| 2026-01-02 | Rename variables to be more clear, document | uvok |
| 2026-01-02 | Add nandgame computer | uvok |
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |