| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2026-01-18 | counter: Add "count_enable" pin | uvok | |
| 2026-01-16 | (System)Verilog: Be explicit about wire/logic | uvok | |
| 2026-01-11 | Use sync output for ROM | uvok | |
| 2026-01-11 | CPU: Annotate unconnected pin | uvok | |
| 2026-01-11 | Dumpfile on VERILATOR | uvok | |
| get rid of VERILATE | |||
| 2026-01-10 | Implement halting | uvok | |
| 2026-01-09 | move stuff around | uvok | |
| 2026-01-07 | Annozate stuff for verilator | uvok | |
| publicly accessible | |||
| 2026-01-06 | use full address space | uvok | |
| 2026-01-02 | Rename variables to be more clear, document | uvok | |
| 2026-01-02 | Add nandgame computer | uvok | |
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |