| Age | Commit message (Expand) | Author |
|---|---|---|
| 7 days | (System)Verilog: Be explicit about wire/logic | uvok |
| 2026-01-06 | include guards | uvok |
| 2026-01-02 | Rename variables to be more clear, document | uvok |
| 2026-01-01 | fix cunter, add testbench | uvok |
| 2026-01-01 | Add counter | uvok |
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |