| Age | Commit message (Expand) | Author |
|---|---|---|
| 2026-01-16 | (System)Verilog: Be explicit about wire/logic | uvok |
| 2026-01-15 | hack: Fix verilator annotation | uvok |
| 2026-01-11 | fix alu: bit negate | uvok |
| 2026-01-11 | implement hack alu | uvok |
| 2026-01-10 | Docu | uvok |
| 2026-01-10 | Add WIP hack ALU | uvok |
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |