| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 7 days | (System)Verilog: Be explicit about wire/logic | uvok | |
| 8 days | hack: Fix verilator annotation | uvok | |
| 12 days | fix alu: bit negate | uvok | |
| 12 days | implement hack alu | uvok | |
| 13 days | Docu | uvok | |
| 13 days | Add WIP hack ALU | uvok | |
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |