| Age | Commit message (Expand) | Author |
|---|---|---|
| 2026-01-16 | (System)Verilog: Be explicit about wire/logic | uvok |
| 2026-01-10 | Implement halting | uvok |
| 2026-01-06 | include guards | uvok |
| 2026-01-02 | Rename variables to be more clear, document | uvok |
| 2026-01-02 | finish instruction decoder | uvok |
| 2026-01-01 | add instruction decoder | uvok |
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index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |