| Age | Commit message (Expand) | Author |
|---|---|---|
| 7 days | (System)Verilog: Be explicit about wire/logic | uvok |
| 2026-01-02 | Rename variables to be more clear, document | uvok |
| 2026-01-02 | Fix verilator multi-module warning | uvok |
| 2026-01-02 | docu | uvok |
| 2026-01-01 | Add nandgame files | uvok |
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |