fpga-exper - FPGA experiments

Age	Commit message (Expand)	Author
18 hours	Reorganize cpp files	uvok
32 hours	dias: Only return halt for simplified	uvok
40 hours	Fixup order/break point	uvok
40 hours	don't draw / refresh UI after a halt	uvok
40 hours	sim: Properly display results	uvok
42 hours	example: Make sure state is shown	uvok
42 hours	main: Write tracefile	uvok
42 hours	verilator: Enable tracing	uvok
42 hours	Implement halting	uvok
42 hours	Docu	uvok
42 hours	Add WIP hack ALU	uvok
2 days	Add assembler exampel	uvok
2 days	bit 14 unset (w/ 15 set) = illegal ins	uvok
2 days	simu: longer simu, stop condition	uvok
2 days	ncur: print instruction across whole line	uvok
2 days	Add LLM assembler	uvok
3 days	make: Unified makefile	uvok
3 days	move stuff around	uvok
3 days	Extract UI drawing	uvok
3 days	include ALU in output	uvok
3 days	Add really nice ncurses UI	uvok
3 days	nandgame: ncurses interface	uvok
3 days	disas, c: Fix compilation, missing header	uvok
3 days	makefile: Add instruction for simulated PC	uvok
4 days	Add cmp instruction	uvok
4 days	disas: endianness	uvok
4 days	cb: specify endianness via arg	uvok
4 days	fix endianness of binary creator	uvok
4 days	Use gen'ed disaas	uvok
4 days	add LLM-gened disas	uvok
4 days	view result register	uvok
4 days	add computer launcher	uvok
4 days	py: Add single-instruction disas	uvok
4 days	disas: Fix for ye olde pyhton	uvok
4 days	Annozate stuff for verilator	uvok
5 days	Documentation	uvok
6 days	disas: Fix fixups	uvok
6 days	test bench for comb_mem	uvok
6 days	use full address space	uvok
6 days	make: Use variables for suffixes	uvok
6 days	include guards	uvok
7 days	disas: Canonocalize AND dest, #0... to mov	uvok
7 days	Canonicalize ops	uvok
7 days	Nicer disas output	uvok
7 days	Improve assembler syntax	uvok
7 days	docu	uvok
7 days	createbin: avoid reserved bits	uvok
7 days	Add disas tests	uvok
7 days	finish disassembler	uvok
7 days	finish disasseembler	uvok