fpga-exper - FPGA experiments

Age	Commit message (Collapse)	Author
8 days	createbin: avoid reserved bits	uvok
	skip in loop, to avoid duplicates
8 days	Add disas tests	uvok

8 days	finish disassembler	uvok

8 days	finish disasseembler	uvok

8 days	disas: move arg check in main	uvok

8 days	black format	uvok

8 days	disas: lowercase ops, arg decode	uvok
	main
8 days	decode op and jumps	uvok

8 days	Start by bin creator and disassembler	uvok

8 days	ins: Add flags to docu	uvok

8 days	finish instruction decoder testbench	uvok

9 days	document nandgame/HACK	uvok

9 days	id testbench	uvok

9 days	Rename variables to be more clear, document	uvok

10 days	prepare instruction decode tb	uvok

10 days	Add nandgame computer	uvok

10 days	Fix verilator multi-module warning	uvok

10 days	docu	uvok

10 days	finish instruction decoder	uvok
	support immediates
11 days	add instruction decoder	uvok

11 days	fix verilator fuckup	uvok
	some recent version of verilator in oss-cad-build-suite started adding_tb to the filename.
11 days	try to implement comb_mem	uvok

11 days	don't delete vvp files	uvok

11 days	fix cunter, add testbench	uvok

11 days	Add counter	uvok

11 days	Add nandgame condition check	uvok

11 days	Update,implement ALU test	uvok

11 days	alu: Fix assignment error	uvok

11 days	include types in tbs again	uvok

11 days	Invert u	uvok

11 days	add ALU	uvok

11 days	fix comment	uvok

11 days	guard types	uvok

11 days	Add arithmetic unit, disable gtkwave	uvok

11 days	Add nandgame files	uvok
	need/want systemverilog
11 days	Add nandgame save	uvok