fpga-exper - FPGA experiments

Age	Commit message (Collapse)	Author
11 days	fix verilator fuckup	uvok
	some recent version of verilator in oss-cad-build-suite started adding_tb to the filename.
11 days	try to implement comb_mem	uvok

11 days	don't delete vvp files	uvok

11 days	fix cunter, add testbench	uvok

11 days	Add counter	uvok

11 days	Add nandgame condition check	uvok

11 days	Update,implement ALU test	uvok

11 days	alu: Fix assignment error	uvok

11 days	include types in tbs again	uvok

11 days	Invert u	uvok

11 days	add ALU	uvok

11 days	fix comment	uvok

11 days	guard types	uvok

11 days	Add arithmetic unit, disable gtkwave	uvok

11 days	Add nandgame files	uvok
	need/want systemverilog
11 days	Add nandgame save	uvok