fpga-exper - FPGA experiments

Age	Commit message (Collapse)	Author
16 hours	Add ROM window	uvok

16 hours	Fixup order of refresh/delay	uvok

16 hours	Add window for clk/regs	uvok

16 hours	reformat code	uvok

16 hours	Split off pure terminal output	uvok

16 hours	Start adding/using windows	uvok

17 hours	Getting started with windows	uvok

17 hours	Add FLTK option, don't hard-define NCUR in source	uvok

17 hours	Fix format specifier	uvok

17 hours	key handling, print finish in bold	uvok

19 hours	ui: Remove remaining define	uvok

19 hours	Print RAM contents and specify memory context size	uvok

19 hours	Print finish message in the top	uvok

19 hours	Use control flow for halting	uvok

19 hours	Show ROM, hide ALU	uvok

19 hours	Remove "offset" variable	uvok

19 hours	Add third assembler example	uvok

19 hours	Use sync output for ROM	uvok

19 hours	CPU: Annotate unconnected pin	uvok

19 hours	Mark to-store registers	uvok

19 hours	ui: don't halt early (refresh UI)	uvok

19 hours	get rid of complicated format specifiers	uvok

19 hours	ui: Fix x/y	uvok

19 hours	comb_mem: Use async data o	uvok

19 hours	Add second example	uvok

20 hours	comb_mem: Test when output occurs	uvok

20 hours	cmake: Gen compile commands	uvok

20 hours	computer: get rid of i	uvok

20 hours	properly use cmake as mentioned in the docs	uvok

20 hours	Utilize cbreak mode	uvok

20 hours	fix olde makefile	uvok

20 hours	Add paused state, print help	uvok
	fix separate "wait for feedback"
20 hours	Rename functions	uvok

20 hours	Improve Cmake file	uvok
	use proper scoping and package finding.
20 hours	Move finish into UI	uvok

21 hours	Move around stuff, split UI	uvok

21 hours	Add cmake build for verilator	uvok

21 hours	Dumpfile on VERILATOR	uvok
	get rid of VERILATE
21 hours	Reorganize cpp files	uvok

35 hours	dias: Only return halt for simplified	uvok

43 hours	Fixup order/break point	uvok

43 hours	don't draw / refresh UI after a halt	uvok

43 hours	sim: Properly display results	uvok
	since halt somehow erases everything directly at the falling egde (WTF?), make two ticks per instructions, and display before and after eval.
46 hours	example: Make sure state is shown	uvok

46 hours	main: Write tracefile	uvok

46 hours	verilator: Enable tracing	uvok

46 hours	Implement halting	uvok

46 hours	Docu	uvok

46 hours	Add WIP hack ALU	uvok

3 days	Add assembler exampel	uvok