| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 26 hours | p2s: Rename input, improve latency | uvok | |
| start clock out data right away. | |||
| 28 hours | Testbench: turn send bit off | uvok | |
| 28 hours | Add quick-and-dirty serial/parallel converters | uvok | |
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |
path: root/par_to_ser.tb.v