| Age | Commit message (Expand) | Author |
|---|---|---|
| 9 hours | p2s: rewrite logic | uvok |
| 9 hours | Re-iterate par2ser | uvok |
| 24 hours | p2s: Fix logic and reset initialization | uvok |
| 24 hours | p2s: Rename input, improve latency | uvok |
| 26 hours | continue complaining | uvok |
| 26 hours | Complain about timing | uvok |
| 26 hours | Add quick-and-dirty serial/parallel converters | uvok |
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |
path: root/par_to_ser.v