| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 10 hours | p2s: rewrite logic | uvok | |
| split blocks. Better separate counting/sending logic. | |||
| 11 hours | Re-iterate par2ser | uvok | |
| 26 hours | p2s: Fix logic and reset initialization | uvok | |
| also, don't use blocking assignments | |||
| 26 hours | p2s: Rename input, improve latency | uvok | |
| start clock out data right away. | |||
| 28 hours | continue complaining | uvok | |
| 28 hours | Complain about timing | uvok | |
| 28 hours | Add quick-and-dirty serial/parallel converters | uvok | |
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |
path: root/par_to_ser.v