fpga-exper - FPGA experiments

Age	Commit message (Collapse)	Author
15 hours	p2s: Always use correct shift width	uvok

15 hours	p2s: rewrite logic	uvok
	split blocks. Better separate counting/sending logic.
16 hours	Re-iterate par2ser	uvok

31 hours	p2s: Fix logic and reset initialization	uvok
	also, don't use blocking assignments
31 hours	p2s: Rename input, improve latency	uvok
	start clock out data right away.
33 hours	continue complaining	uvok

33 hours	Complain about timing	uvok

33 hours	Add quick-and-dirty serial/parallel converters	uvok